1. Field of the Invention
The present invention relates generally to automatic integrated-circuit placement and routing tools, and more particularly to symbolic constraint-based systems for preroute reconstruction following floorplan incrementing.
2. Description of the Prior Art
After the logic circuitry for a very large scale integrated (VLSI) circuit has been designed, placement "algorithms", really computer-implemented processes, are used to "place" each circuit macrocell of the VLSI circuit logic in the floorplan of an integrated circuit (IC) chip. Computer-implemented processes, called "routers", are used to interconnect the macrocells into wire networks, e.g., "nets". Local bundles of these connection networks have a measurable width and take up space on the integrated circuit. Too many connections may be attempted through a bundle that passes between macrocells, and this can stymie the automatic design by becoming congested.
Preferably, the locations selected for each macrocell and the wire routing choices have been optimal. An acceptable placement of component blocks occurs when the unused space between component blocks is at a minimum, and when the overall area used for the whole design is minimized.
Beyond the wire connection of functional networks that provide the various signal paths within an IC, it is also necessary to route special wire networks, e.g., ground, power and clocks. See, Andrew S. Moulton, "Laying the Power and Ground Wires on a VLSI Chip", 20th Design Automation Conference, IEEE, 1983, pp. 754-755; and, David W. Russell, "Hierarchical Routing of Single Layer Metal Trees in Compiled VLSI", ICCAD, IEEE, 1985, pp. 270-272. The special connections of power and ground are needed by just about all the active cells in a device, and their connection can sometimes compete with the required signal net connections.
Daniel R. Brasen describes, in U.S. Pat. No. 5,485,396, issued Jan. 16, 1996, a floorplan of component blocks of logical circuits, including the symbolic routing of major connection networks, which is produced as part of the process for laying out an integrated circuit on a chip. The floorplan is done before optimized placement and routing of the logical circuits within the individual component blocks of the VLSI circuit. The logical circuits are apportioned into component blocks. Then, an initial layout of the component blocks of the VLSI circuit is made. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial layout of the component blocks is adjusted, as necessary, to take into account the addition of the major connection networks. Then, routing guidance information is generated as part of the floorplan. The routing guidance information indicates locations and sizes of each of the major connection networks.
Daniel R. Brasen also describes, in U.S. Pat. No. 5,349,542, issued Sep. 20, 1994, the calculating of segments within a power network of an integrated circuit using information generated during design and placement. The performance of logic blocks within the integrated circuit is simulated to obtain an estimated maximum current requirement for each logic block. After estimating the maximum current requirement for each logic block, the maximum current flow through each power net segment is obtained by summing the current requirements for each logic block which draws current through the power net segment. Based on this maximum current flow through each power segment, the width for each power net segment is calculated. A check may be made to assure that a predetermined electromigration limit is not exceeded. When the projected current flow through a power net segment exceeds the predetermined electromigration limit, the width of the power net segment is increased.
Steven L. Crain, et al., describes in U.S. Pat. No. 5,311,443, issued May 10, 1994, a rule-based floorplanner for a macrocell array comprising a plurality of predetermined macrocells. The floorplanner uses a net list, a macrocell list, and a list of design constraints and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted and checked against a list of theoretical rules and a list of empirical rules to determine a measured Burain score which accurately indicates the difficulty which can be expected when completing the design.
For the physical design of very large scale integration (VLSI) chips, Klein, et al., describes a method for implementing a high density master image of logic, e.g., in U.S. Pat. No. 4,890,238, issued Dec. 26, 1989. In a hierarchical top-down design methodology, the chip circuitry is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are included in the initial design of the different individual partitions and treated there in the same way as circuits in that area. The various partitions are designed in parallel. A floorplan is established that provides the different partitions shaped in such a way that they fit together without leaving any space between the different individual partitions.
Conventional design approaches begin with a fixed core area and place the various blocks (macrocells) within the floorplan. The rest of the core area is then used for the placement of standard cells. If the floorplan is not just right, local congestion of routing resources can lead to incomplete connections. Getting stuck this way necessitates re-running the placement and routing processes. Several such iterations may be required with intermediate fudging by the user before 100% routing completion is obtained. using core areas larger than actually required can solve the completion problem, but wastes considerable floorplan area.
Multiple place and route passes waste time. Each pass must necessarily redo all the special routing too, e.g., power, ground, and clock prerouting for each floorplan change. Since such prerouting usually needs considerable user intervention, especially when the design has several macrocell blocks, the turnaround time can be considerably extended for each additional pass. Ignoring the special prerouting before doing the floorplan is not possible, since the placement and routing are so greatly impacted.